Silicon on insulator (SOI) wafers are becoming an increasingly accepted form of silicon wafers for the manufacture of semiconductor devices. SOI wafers have a thin layer of silicon dioxide below the surface of the single crystal silicon wafer. This layer electrically isolates the surface layer from the bulk of the wafer and allows semiconductor devices to operate at higher speeds with lower power consumption. Thus, the wafer structure consists of a top single crystal silicon layer (the device layer), an amorphous silicon dioxide layer (the buried oxide or BOX layer), and a substrate or handle wafer. The handle wafer is typically a single crystal silicon wafer. A typical wafer structure is shown in FIG. 1 in which layer 1 is the top silicon layer, called the device layer wherein the semiconductor device is fabricated; layer 2 is the BOX or insulator layer; and layer 3 is the substrate.
Power dissipation in a semiconductor device is limited by the thermal conductivity of the materials from which it is made. This thermal conductivity in turn limits the packing density of the transistors on a semiconductor wafer or the amount of power that can be generated in a circuit without inducing circuit failure. Thus, one side effect of electrically isolating the top silicon layer with silicon dioxide is that the top layer is also thermally insulated from the silicon substrate. This accentuates the self-heating of circuits and can cause problems with high power devices such as microprocessors. Several designs have been proposed to overcome the detrimental effects of this thermal isolation including the use of local thermal paths to transport the heat through the oxide layer or the fabrication of a “partial” SOI wafer having areas of wafer without an oxide layer.
These designs are difficult and therefore expensive to implement. A novel solution provided by this invention is the use of high thermal conductivity silicon-28 in the manufacture of SOI wafers. By utilizing an isotopically-enriched silicon-28 device layer and/or an isotopically-enriched silicon-28 layer under the oxide, lateral heat spreading can be maximized. This is particularly true for thin-film SOI wafers where the top silicon layer is much less than one micron thick. With these wafers, the device layer can be natural silicon since the thermal transport in the device layer is controlled by interface scattering effects and not by the bulk properties of the silicon. In this case an underlayer of isotopically-enriched silicon helps greatly to spread the heat generated in the device layer. Silicon-28 can be incorporated without changing the device design and at relatively modest cost since the amount of silicon-28 in these thin layers is small. Fabricating isotopically modified SOI wafers allows for increased power densities in these devices, thereby enhancing the performance of many electronic devices now on the market.